1. Field of the Invention
The present invention relates to a bi-polar transistor structure constituting an active element in a superhigh speed logic integrated circuit, and a process for producing the same.
2. Prior Art
In general, ECL (emitter coupled logic) circuits are used as superhigh speed logic integrated circuits. The following two requirements in the parameters of transistors incorporated into an ECL circuit may be mentioned, in a rough sense, for improving the operational speed of the ECL circuit. One requirement is to reduce the parasitic capacitance and parasitic resistance of a transistor, which are transistor parameters as circuit constants, while the other requirement is to improve the cut-off frequency f.sub.T of the transistor, which is a major parameter affecting the performance of the transistor. Factors in the transistor that are important to meet the above-mentioned requirements include the base resistance r.sub.bb ', the collector saturation resistance r.sub.CS, the base-collector junction capacitance c.sub.TC, the collector-substrate junction capacitance c.sub.TS, and the effective base width W.sub.B. These factors are all desired to be minimized. Among others, however, the influences of c.sub.TC and W.sub.B are large. Since the c.sub.TC is a factor that not only adversely affects the parasitic capacitance of a circuit but also holds down the f.sub.T, a reduction in the c.sub.TC is important in an aspect of the transistor itself as well as in an aspect of the circuit
As for the W.sub.B, f.sub.T rises in reverse proportion to the square of the W.sub.B, which may therefore be highly contributory as compared to the other factors. Thus, the W.sub.B is an important factor as well.
From the above-mentioned point of view, the conventional approaches to an improvement in the above-mentioned operational speed have placed emphasis on the base region of a transistor in most cases. Specifically, those approaches include provision of a shallow junction between an active base layer and a collector layer (reduction in effective base width W.sub.B) and a reduction in an outer base region (decrease in base-collector junction capacitance c.sub.TC), on the two of which great emphasis has been placed.
Since the reduction in the size of a transistor resulting from the above-mentioned approaches concurrently contributes to an improvement in the scale of integration of an integrated circuit, however, an integrated circuit is inevitably scaled up in the integration thereof to incur an increase in the power consumption thereof Such an increase in power consumption of an integrated circuit brings about various problems, including a decrease in the reliability of transistors incorporated into the integrated circuit because of an increase in the electric current density through wirings in the circuit, and changes in the characteristics of the circuit because of heat build-up therein. Therefore, the performance of a transistor must be such that a high operational speed can be secured with a low operational electric current. When the above-mentioned transistor parameters are examined from this point of view, it will be apparent that a reduction in the collector substrate junction capacitance c.sub.TS is important in addition to reductions in the base-collector junction capacitance c.sub.TC and the effective base width W.sub.B.
A description will be made of a technique developed from this point of view which is disclosed in Japanese Patent Publication No. 54,255/1986. FIGS. 1(a) to 1(h) are cross-sectional views of major structures in the steps of production of a bi-polar transistor structure according to the process disclosed in this patent literature as one example of conventional processes.
First, as shown in FIG. 1(a), an oxide layer 202 formed on the whole surface of a substrate 201 is subjected to patterning to expose a surface area of the substrate 201 having thereon a hole 201a to constitute a single crystal region wherein a transistor is to be formed.
Subsequently, as shown in FIG. 1(b), an n-type impurity or dopant is diffused into the substrate 201 from the above-mentioned exposed surface area thereof to form an embedded collector layer 203. Meanwhile, a p.sup.+ -type region 204 is a p.sup.+ -type channel cut region provided in a surface portion of the p-type substrate 201 and in a region thereof other than the n.sup.+ -type embedded region.
Thereafter, as shown in FIG. 1(c), n-type epitaxial growth is effected to form a single crystal layer 205a on the exposed surface area of the substrate 201 having thereon the hole 201a to constitute the single crystal region and a polycrystalline layer 205b on the oxide layer 202.
Subsequently, as shown in FIG. 1(d) a p-type impurity or dopant is diffused through the whole upper surface under predetermined conditions to form p-type regions 251a and 251b differing thickness because of a difference in the diffusion coefficient of the impurity or dopant between the single crystal layer 205a and the polycrystalline layer 205b.
Thereafter, as shown in FIG. 1(e), etching back is effected by dry etching using a mixed gas of CF.sub.4 +O.sub.2 to substantially planarize the whole upper surface by virtue of the dependency of etching on impurity or dopant concentration.
The succeeding steps, for the details of which reference may as well be made to the aforementioned patent literature, are simply illustrated in FIGS. 1(f) and 1(g) 1(h) showing an active base layer 207a, an outer base region 207b, a base electrode 211c, a collector sink region 209a, a collector electrode 209b, and an emitter layer 210, which are formed using known photoetching and impurity or dopant diffusion techniques. In FIG. 1(h) numerals 211a and 211b refer to another collector electrode and an emitter electrode, respectively.
The foregoing conventional process has a feature that the use of the microphtoetching technique enables both of the base-collector junction capacitance c.sub.TC and the collector-substrate junction capacitance c.sub.TS of the resulting bi-polar transistor to be lowered with the value of c.sub.TS being extremely low as compared with that of an isoplanar transistor produced at the same level of fineness as in the case of the above-mentioned process.
Since patterning of the emitter region and the base region is effected by the photoetching technique in the above-mentioned conventional process for producing the bi-polar transistor, however, the fineness of the resulting circuit is restricted by minimum resolution and minimum registration accuracy inherent in the photoetching technique.
Therefore, there arises a problem that, compared with an isoplanar transistor produced at the same level of fineness as in the case of the above-mentioned process, reductions in the base resistance r.sub.bb ' and the base-collector junction capacitance c.sub.TC of the bi-polar transistor are impossible through a reduction in the collector-substrate junction capacitance c.sub.TS of the bi-polar transistor is possible.
Further, since the base and collector electrodes are provided only on one side of the active layer according to the above-mentioned conventional process, reductions in the collector saturation resistance r.sub.CS and the base resistance r.sub.bb ', which are the series resistance components of the base and the collector, respectively, are restricted.
In addition to the above-mentioned problems, the surface of the polycrystalline silicon base electrode and the surface of the polycrystalline silicon collector electrode are covered uniformly with silicon oxide films to require a so-called "contact step" (step of forming contact holes) of perforating the silicon oxide films by a photoetching technique to connect the electrodes to a wiring pattern in the course of formation of an integrated circuit. This will make the dimensional accuracy and the registration accuracy in the contact step restrictive factors in improving the overall operational speed of the integrated circuit by raising the scale of integration of the circuit to minimize the retardation of the circuit operation attributed to wirings.